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Preliminary Information
64K
X46402
Dual Voltage CPU Supervisor with 64K Password Protected EEPROM
DESCRIPTION
The X46402 combines several functions into one device. The first is a dual voltage CPU supervisor plus 64Kbit serial EEPROM memory with password protected write and read operations. The size of the password protected area is selectable by 3 control bits. A Write Protect (WP) pin in conjunction with a WPEN bit provides hardware OTP control of the configuration of the array. Password protected areas require 64 bit read or write passwords prior to access. The eighth illegal password entry (regardless of the number of correct entries) sets an OTP tamper bit. This bit is one of the 32 bits in the Device ID. A secondary voltage monitor circuit activates a V2FAIL pin when the secondary supply voltage drops below a V2trip voltage. This circuit is primarily intended to detect the immediate loss of the battery supply. A low Vcc voltage detect circuit activates a RESET pin when Vcc drops below a VTRIP voltage. This signal also blocks read or write operations. A watchdog timer with the time period controlled by three bits provides several possible time out periods from 150ms to 1 minute.
FEATURES * Dual Voltage Detection and Reset Assertion --Low Vcc Monitor --Low V2MON Monitor --Low Vcc Block of EEPROM Writes --RESET Signal Valid down to Vcc=1V * Selectable Watchdog Timer --150ms, 450ms, 1s, 5s, 10s, 20s, 1min, OFF * Volatile Flag shows Watchdog/Low Voltage Reset * 64kbit 2-wire Serial EEPROM --1MHz Serial Interface speed --64-Byte Page Write Mode * Two 64-Byte OTP memory blocks --Requires 64-bit OTP password to write * Adjustable size Password Protected Array --64 Bit Read and Write Array Passwords --Non-password protected array area * 8 count tamper counter for invalid passwords * Operates at 2.5-3.7V * 8L TSSOP package
Functional Diagram
WP Write Control Password Logic HV Generation Timing and Control
WATCHDOG TIMER RESET
RESET & WATCHDOG TIMEBASE
RESET
SCL SDA
Command Decode and Control Logic
EEPROM Array (64Kbits)
X Decoder
Write Password Area (Bytes) (64, 128, 256, 512, 2K, 4K, All, None) No Password Area Control OTP array 1 OTP array 2 Passwords Y Decoder Data Register
POWER ON AND LOW VOLTAGE RESET GENERATION
V2FAIL
+ -
V2MON
V2TRIP
(Vcc) Control Signal
+ -
Vcc
VTRIP
(c)Xicor, Inc. 1994, 1995, 1996, 1998 Patents Pending 9900-3003 5 1/11/00 CM
1
Characteristics subject to change without notice
X46402
PACKAGE/PINOUTS
8L TSSOP
Preliminary Information
sense level. It will remain active until V2MON rises above the minimum V2MON sense level.
VSS WP SDA RESET
1 2 3 4
8 7 6 5
VCC V2MON SCL V2FAIL
DEVICE OPERATION Power On Reset Application of power to the X46402 activates a Power On Reset Circuit. This circuit goes active at 1V and pulls the RESET pin active. This signal prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. When Vcc exceeds the device VTRIP value for 200ms (nominal) the circuit releases RESET allowing the processor to begin executing code. Low Voltage Monitoring During operation, the X46402 monitors the VCC and V2MON levels and compares these with internal, preset voltages. When the internal low voltage detect circuitry senses that V2MON is low, the V2FAIL pin goes active. Typically this would be used by the processor as an interrupt to stop the execution of the code or to do housekeeping in preparation for an impending power failure. When the internal low voltage detect circuitry senses that Vcc is low, the following happens: --The RESET pin goes active. --The Flag bit in the control register is set to zero. --Communication to the device is interrupted and any command is aborted. If a serial nonvolatile store is in progress when power fails, the circuitry does not stop the nonvolatile store operation, but attempts to complete the operation. The RESET and V2FAIL signals remain active until Vcc voltage drops below 1V. RESET remains active until Vcc returns and exceeds VTRIP for 200ms. V2FAIL remains active until immediately after V2MON returns and exceeds it's minimum voltage. Watchdog Timer The Watchdog Timer circuit monitors the microprocessor activity by monitoring the Start bit. The microprocessor must send a start bit periodically to prevent a RESET signal. The start bit must occur prior to the expiration of the watchdog time-out period. The state of three nonvolatile control bits in the Control Register determines the watchdog timer period. The microprocessor can change these watchdog bits, or they may be "locked" by tying the WP pin HIGH and setting the WPEN bit HIGH.
PIN NAMES VSS SDA VCC SCL WP V2MON RESET V2FAIL Ground Serial Data Power Serial Clock Write Protect Voltage monitor input Low Voltage Detect Output V2 Voltage Fail Output
PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with other open drain or open collector outputs. An open drain requires the use of a pull-up resistor. Write Protect (WP) The WP pin works in conjunction with a nonvolatile WPEN bit to "lock" the setting of the Watchdog Timer control and the memory write protect bits. Reset Output (RESET) RESET is an active LOW, open drain output which goes active whenever Vcc falls below the minimum Vtrip sense level. It will remain active until Vcc rises above the minimum Vtrip sense level for 150ms. RESET goes active if the Watchdog Timer is enabled and there is no start bit before the end of the selectable Watchdog time-out period. A serial start bit will reset the Watchdog Timer. RESET also goes active on power up at 1V and remains active for 150ms after the power supply stabilizes. V2 Voltage Fail Output (V2FAIL) V2FAIL is an active LOW, open drain output which goes active whenever V2MON falls below the minimum V2trip
2
X46402
C Volt Reg
OTP Mode Enabled
Preliminary Information
The Control Register contains bits that control the watchdog timer and the hardware write protect features and is formatted as follows:
7 6 5 4 3 2 BL2 1 BL1 0 BL0
Vcc
Pin1 Vss WP SDA RESET
Vcc V2MON SCL V2FAIL
WPEN FLB
SCL SDA INTR RESET
WD2 WD1 WD0
Recommended Connection ARCHITECTURE Data Memory This 64kbit memory array can be partitioned into password protected or non-password protected areas. When password protected, the contents are readable after sending a "Memory Read" password. The contents of a password protected portion of the memory array are writeable with a "Memory Write" Password. This array is re-writable up to the limit of the EEPROM endurance. OTP The second section of memory consists of two 64-byte arrays, each writable only once. These arrays are always password protected. Reading from either of these arrays requires the use of an "OTP Read" password. Both arrays can be read with a single operation. Writing either array requires an "OTP Write" Password. Writing more than 64 bytes to each array results in the data "wrapping" around and over-writing previous values. Array
OTP Array 1 OTP Array 2
Write Protect Enable bit (WPEN) The WP pin, in conjuction with a WPEN bit programmed HIGH, provides Hardware Write Protection. This prevents changes to the control register contents even with a valid password. When either the WP pin or WPEN bit is LOW, a 64 bit Array write array password is required to change the contents of the control register. When both the WP pin and the WPEN bit are HIGH, the Control Register cannot be written. Flag Bit The flag bit is a volatile bit. It can be used to determine if a reset condition was due to a power failure or watchdog reset condition. If power fails (i.e. the internal low voltage detect signal goes active), the bit is set to '0'. This bit is also set or reset by a Control Register write operation. A watchdog reset does not change the state of the flag bit. Watchdog Timer Control The Watchdog time-out period is controlled by the bits WD2, WD1, and WD0. See the following Table. Table 1. Watchdog Time Control Bits Control Register Bits WD2 WD1 WD0
0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
Watchdog Time-out (Typical)
1 Second 450 Milliseconds 150 Milliseconds Disabled 1 minute 20 seconds 10 seconds 5 seconds
Address
0000h - 003Fh 0040h - 007Fh
Control Register A password protected read or write array command at address FFFFh reads or writes the Control Register. Since the control register contains information relating to the password protection, it is necessary to use the Array passwords to access the control register.
3
X46402
Password Protection Configuration Portions of the memory array may be "locked". This area of memory is password protected and is defined by the bits BL2, BL1 and BL0. For these protected areas it is necessary to use a Read password to output data and an "Array Write" Password to write data. This block lock area is re-writable, by issuing the correct password. Table 2. Password Protected Block Size Select BL2 BL1 BL0
000 001 010 011 100 101 110 111
Preliminary Information
If the X46402 is in a nonvolatile write cycle a "no ACK" (SDA=HIGH) response will be issued in response to loading of the command byte. If a stop is issued prior to the start of a nonvolatile write cycle the write operation will be terminated and the part will reset and enter into a standby mode. The basic sequence is illustrated in Figure 1. After each transaction is completed, the X46402 will reset and enter into a standby mode. This will also be the response if an unsuccessful attempt is made to access a protected array. Password Protection The X46402 requires a 64 bit write password to change the contents of the control register or to write to a block protected memory area. The X46402 also requires a 64 bit read password to output the contents of the block protected array or the control register. The block protection is controlled by the [BL2:BL0] bits and allows the options described in Table 2. If an area is block protected, it needs a password prior to each read or write to the area. The passwords cannot be read, even after the device receives the correct password. Figure 1. X46402 Device Operation (Password Protected Areas)
LOAD COMMAND BYTE
Password Protected Addresses
(Use Password Command)
Non-Password Protected Addresses
(Use Password or No-Password Commands)
None 0000h - 003Fh 0000h - 007Fh 0000h - 00FFh 0000h - 01FFh 0000h - 07FFh 0000h - 0FFFh 0000h - 1FFFh
0000h - 1FFFh 0040h - 1FFFh 0080h - 1FFFh 0100h - 1FFFh 0200h - 1FFFh 0800h - 1FFFh 1000h - 1FFFh None
SERIAL MEMORY OPERATION There are four primary modes of operation for the X46402; Protected READ and WRITE of the memory and OTP arrays and unprotected Read and Write of nonpassword protected areas of the memory array. Protected operations must be performed with one of four 8byte passwords. The basic method of communication for the password protected areas of the device is established by generating a start condition, then transmitting a command, followed by the correct password. All parts will be shipped from the factory with all passwords equal to `0'. The user must perform ACK Polling to determine the validity of the password, before starting a data transfer (see Acknowledge Polling.) Only after the correct password is accepted and a ACK polling has been performed, can the data transfer occur. Non-password protected areas of the memory array are accessed in the same manner as access to password protected areas, except the password and the password acknowledge polling sequences are not required. Data is transferred in 8-bit segments, with each transfer being followed by an ACK, generated by the receiving device.
LOAD 8-BYTE PASSWORD
VERIFY PASSWORD ACCEPTANCE BY USE OF PASSWORD ACK POLLING
LOAD 2 BYTE ADDRESS
READ/WRITE DATA BYTES
Twc OR DATA ACK POLLING
4
X46402
Figure 2. Set VTRIP Level Sequence (VCC VTRIP)
VCC VTRIP
Preliminary Information
RESET
VP = 15V
0 1 234 56 7
0 1 234 56 7
SCL
0 1 234 56 7
SDA
D8h
00h
01h
01h sets Vcc
Figure 3. Set V2TRIP Level Sequence (VCC V2TRIP)
V2TRIP V2MON
RESET
VP = 15V
0 1 234 56 7
0 1 234 56 7
SCL
0 1 234 56 7
SDA
D8h
00h
0Dh
0Dh sets V2MON
Figure 4. Reset VTRIP Level Sequence (Vcc > 3V, WEL is set.)
VCC
VTRIP RESET
VP = 15V
0 1 234 56 7 0 1 234 56 7 0 1 234 56 7
SCL
SDA
D8h
00h
03h
03h resets Vcc
5
X46402
Figure 5. Reset V2TRIP Level Sequence (Vcc > 3V, WEL is set.)
V2TRIP V2MON RESET
Preliminary Information
VP = 15V
0 1 234 56 7 0 1 234 56 7 0 1 234 56 7
SCL
SDA
D8h
00h
0Fh
0Fh resets V2MON
VCC AND V2MON THRESHOLD RESET PROCEDURE The X46402 is shipped with standard VTRIP, and V2TRIP voltages. These values will not change over normal operating and storage conditions. However, in applications where the standard thresholds are not exactly right, or if higher precision is needed in the threshold value, the X46402 trip points may be adjusted. The procedure is described below, and uses the application of a high voltage control signal. Setting the VTRIP Voltage This procedure is used to set the VTRIP,V2TRIP to a higher voltage value. For example, if the current VTRIP is 4.4V and the new VTRIP is 4.6V, this procedure will directly make the change. If the new setting is to be lower than the current setting, then it is necessary to reset the trip point before setting the new value. To set the new voltages, apply the desired VTRIP threshold voltage to the Vcc pin, the V2TRIP voltage to the V2MON pin, then tie the RESET pin to the programming voltage VP. Then, write data 01h or 0Dh address 00h to Figure 6. Sample VTRIP Reset Circuit
program VTRIP, V2TRIP respectively. The stop bit following a valid write operation initiates the programming sequence. Bring RESET LOW to complete the operation. Note: this operation also writes 01h, or 0Dh to address 00h. Resetting the VTRIP Voltage This procedure is used to set the VTRIP, the V2TRIP to a "native" voltage level. For example, if the current VTRIP is 4.4V and the new VTRIP must be 4.0V, then the VTRIP must be reset. When the threshold is reset, the new level is something less than 1.7V. This procedure must be used to set the voltage to a lower value. To reset the new VTRIP, V2TRIP voltage, apply the desired VTRIP or V2TRIP threshold voltage to the Vcc or V2MON pin, respectively, and tie the RESET pin to the programming voltage VP. Then write 03h or 0Fh to address 00h. The stop bit of a valid write operation initiates the programming sequence. Bring RESET LOW to complete the operation. Note: this operation also writes 03h or 0Fh to address 00h of the EEPROM array.
VP V2FAIL RESET VTRIP Adj. V2TRIP Adj. 4.7K Adjust
5 4 7 1 X46402 8 2 6 3
C
Run SCL SDA
6
X46402
Preliminary Information
VTRIP/V2TRIP Programming
Execute Reset VTRIP/V2TRIP Sequence Set Vcc = Vcc applied = Desired VTRIP OR Set V2MON = V2MON applied = Desired V2TRIP, Vcc>=V2Trip
New Vcc or V2MON applied = Old Vcc V2MON applied + Error
Execute Set VTRIP, V2TRIP Sequence Recyle Vcc power Apply 5V to Vcc or V2MON
New Vcc/V2MON applied = Old Vcc applied - Error
Execute Reset V2TRIP, VTRIP Sequence
Decrement Vcc or V2MON (<50mV step)
NO
RESET or V2FAIL pin goes active? YES
Error < 0
Measured V(2)TRIP Desired V(2)TRIP
Error > 0
Error = 0
DONE
7
X46402
Figure 7. X46402 Device Operation (Non-Password Protected Areas)
LOAD COMMAND BYTE
Preliminary Information
After each byte written to or read from the X46402, the address pointer is incremented by 1. This allows the user to read from the entire device after sending only a single address. It also allows an entire page to be written in one operation. An exception to this address incrementation occurs during a read. After reading address 1FFFh the device goes into an idle mode, so additional reads return all "1s". Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figure 8 and Figure 9. Start Condition All commands are preceeded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X46402 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met. A start may be issued to terminate the input of a control byte or the input data to be written. This will reset the device and leave it ready to begin a new read or write command. A start bit generated while the part is outputting data is accepted as a start as long as the device is not outputting a 'zero'. Stop Condition All communications are be terminated by a stop condition. The stop condition is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to reset the device during a command or data input sequence and will leave the device in the standby power mode. As with starts, stops are recognized while the device outputs data, as long as the data output is not a `zero'. Figure 8. Data Validity SCL
LOAD 2 BYTE ADDRESS
READ/WRITE DATA BYTES
Twc OR DATA ACK POLLING
Tamper Counter The X46402 contains a tamper counter. The entry of an invalid password increments the counter. This operation requires an internal nonvolatile cycle, requiring up to 10 ms to complete. To minimize the possibility of of an unauthorized person monitoring the device current to detect the enry of the correct password, an internal high voltage cycle is initiated even when the counter does not increment. As such, each password entry requires up to 10ms to acknowledge, so a long period of time would be required to correctly guess the password. On the eighth incorrect password entry, a one-time programmable tamper bit is set in the Device ID area. The Tamper Counter increments with each incorrect password attempt and cannot be reset, except by the Reset Device Command. When the tamper counter overflows, the device is "locked". In the locked condition, none of the password commands respond except Reset Device. Nopassword commands are always available. The locked condition is determined by reading the device ID and reading bit 32. The device is reset by the Master Reset or Reset Device commands. Device Protocol The X46402 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as a receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X46402 will be considered a slave in all applications.
SDA Data Data Stable Change
8
X46402
Figure 9. Definition of Start and Stop Conditions Acknowledge
SCL SDA Start Condition Stop Condition
Preliminary Information
Read Device ID Command A special, non-password protected command reads the device ID. The device ID is a 32 bit identification code that can be generic or tailored to the needs of an individual company. The last of the 32 bits indicates whether the device has been tampered with by an unauthorized user attempting to enter invalid passwords. Reset Device Command The Reset Device command resets the tamper bit, clears the tamper counter and removes the tamper "lock" (allowing the device to accept commands). However, the Reset Device command does not clear any memory array area.
Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. The X46402 will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write condition have been selected, the X46402 will respond with an acknowledge after the receipt of each subsequent eight-bit word. Table 3. X46402 Instruction Set 1st Byte after Start
1000 0000 1000 1000 1001 0000 1001 1000 1010 0000 1010 1000 1011 0000 1011 1000 1100 0000 1100 1000 1101 1000 1110 1000 1111 0000
1st Byte after Password
High Address High Address High Address High Address 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 High Address High Address not used not used All the rest
2nd Byte after Password
Low address Low address Low address Low address 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Low address Low address not used not used
Command Description
Password Memory Array Read OTP Read Password Memory Array Write OTP Write Change Memory Read Password Change OTP Read Password Change Memory Write Password Change OTP Write Password Change Reset Password No-Password Memory Array Read No-Password Memory Array Write Reset Device Command (Resets Tamper bit) ACK Polling command (Ends Password operation) Reserved
Password used
Memory Read OTP Read Memory Write OTP Write Memory Read OTP Read Memory Write OTP Write Reset None None Reset None
Notes: Illegal command codes will be disregarded. The part will respond with a "no-ACK" to the illegal byte and then return to the standby mode.
9
X46402
PROGRAM OPERATIONS Password Protected Array Programming The password protected memory array write or OTP write requires issuing an 8-bit Password Write command followed by the password, password ACK command, the address and then the data bytes transferred as illustrated in Figure 10. Up to 64 bytes (or more) may be transferred. Sending more than 64 bytes results in data wrapping and over-writing previous data. After the last byte to be transferred is acknowledged, a stop condition is issued which starts the nonvolatile write cycle.
Preliminary Information
Non-Password Protected Array Programming The non-password protected memory array program mode requires issuing the 8-bit No-Password Write command followed by the address and then the data bytes transferred as illustrated in Figure 11. Up to 64 bytes (or more) may be transferred. Sending more than 64 bytes results in data wrapping and over-writing previous data. After the last byte to be transferred is acknowledged a stop condition is issued which starts the nonvolatile write cycle.
Figure 10. Password Protected Array Programming (Memory and OTP arrays)
START Write Password 7 Write Password 0
Password COMMAND
SDA S ACK ACK ACK ACK
Wait tWC OR Repeated ACK Polling Command
If ACK, Then Password Matches START ACK POLLING COMMAND A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 0
S ACK ACK NACK ACK ACK Wait tWC Data ACK Polling
...
Data 63 STOP S ACK ACK
Figure 11. Non-Password Protected Array Programming (Memory array only)
START No Password COMMAND STOP ACK
A15 A14 A13 A12 A11 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
Data 0
Data 63
SDA S ACK ACK ACK ACK
...
ACK
Wait tWC
S Data ACK Polling
10
X46402
ACK Polling Once a stop condition is issued to indicate the end of the host's write sequence, the X46402 initiates the internal nonvolatile write cycle. In order to take advantage of the typical 5ms write cycle, ACK polling can begin immediately. This involves issuing the start condition followed by the new command code of 8 bits (1st byte of the protocol.) If the X46402 is still busy with the nonvolatile write operation, it will issue a "no-ACK" in response. If the nonvolatile write operation has completed, an "ACK" will be returned and the host can then proceed with the rest of the protocol. See Figure 12.
Preliminary Information
Password ACK Polling Sequence
PASSWORD LOAD COMPLETED ENTER ACK POLLING
ISSUE START
ISSUE PASSWORD ACK COMMAND
Data ACK Polling Sequence
WRITE SEQUENCE COMPLETED ENTER ACK POLLING ACK RETURNED? YES ISSUE START PROCEED NO
ISSUE NEW COMMAND CODE
ACK RETURNED? YES PROCEED
NO
If the password that was inserted was correct, then an "ACK" will be returned once the nonvolatile cycle is over, in response to the ACK polling cycle immediately following it. If the password that was inserted was incorrect, then a "no ACK" will be returned even if the nonvolatile cycle is over. Therefore, the user cannot be certain that the password is incorrect until the 10ms write cycle time has elapsed.
After the password sequence, there is always a nonvolatile write cycle. This is done to discourage random guesses of the password if the device is being tampered with. In order to continue the transaction, the X46402 requires the master to perform an ACK polling with the specific code of F0h. As with regular Acknowledge polling the user can either time out for 10ms, and then issue the ACK polling once, or continuously loop as described in the flow.
11
X46402
Figure 12. Acknowledge Polling
Preliminary Information
SCL
8th clk. of 8th pwd. byte
`ACK' clk
8th clk
`ACK' clk
SDA
`ACK' START condition
8th bit ACK or no ACK
PASSWORD PROTECTED READ OPERATIONS Password protected read operations are initiated in the same manner as password protected write operations but with a different command code. Password Random Read (Data Array, OTP Arrays) Data from a password protected array can be randomly read after sending a single password. To do this, the master issues a start bit, sends a Password Read instruction and read password, performs Password Ack Polling, then issues the desired 2 byte address. The host receives the first byte from the X46402 and sends a NACK, followed by a repeated start bit. A new 8-bit address specifies the next byte to read. This process can continue indefinitely as long as the each byte read out of the X46402 is "NACKed" and followed by a repeated start. The address automatically increments after each read operation. As such, a special case arises. A random read of address 00FFh automatically increments to 0100h after reading the byte. Consider the following example. Example: A system needs data from password protected locations 0020h and 0150h and the designer does not wish to send the password twice. After receiving data from 0020h, the host sends a NACK and a repeated start, followed by address byte FFh. The data read from location 0FFh is ignored, but the operation has adjusted the address pointer to 100h. Another NACK and repeated start followed by the address 50h allows the contents of 150h to be read by the host. A random read of either of the OTP arrays can access all locations of both arrays without another password command sequence. A password random read operation will also return valid data if accessing a non-password protected area of the array. See Figure 13.
Password Sequential Read The host can read sequentially within an array after the password acceptance sequence. The data output is sequential, with the data from address n followed by the data from n+1. The address counter for read operations increments all address bits, allowing the entire memory array contents to be serially read during one operation. At the end of the address space (address 1FFFh for the memory array, 7Fh for the OTP array) the device goes into an idle state and data output is all "1s". To continue reading at another address requires a new Read operation. Refer to Figure 14 for the address, acknowledge and data transfer sequence. An acknowledge must follow each 8-bit data transfer. After the last bit has been read, the host sends a stop condition with or without a preceding acknowledge. After sending a Password Read command and the correct password, the entire array, including non-password protected areas will be read with a sequential read command. After sending a Password Array Read command and correct password, the entire array, including non-password protected areas are read by a sequential read command. NON-PASSWORD READ OPERATIONS Non-password protected read operations are initiated in the same manner as non-password protected write operations but with a different command code. No-Password Random Read The master issues the start condition, then a No-password Read instruction, then issues the word address. Once the first byte has been read, another start can be issued followed by a new 8-bit address. A No-Password random read operation is not allowed to a password protected area. In a No-Password Random Read from address 00FFh, the address pointer changes to 100h after outputting the data byte and operates in the same manner as the password protected operation. See Figure 15.
12
X46402
No-Password Sequential Read The host can read sequentially within the un-protected area of the array after receiving the No-password Command and an address within the unprotected address space. The data output is sequential, with the data from address n followed by the data from n+1. The address counter for read operations increments all address bits, allowing the entire un-protected memory array contents to be serially read during one operation. At the end of the address space (address 1FFFh) the device goes into an idle state and a new read sequence must be initiated to continue reading at another address. Refer to Figure 16 for the address, acknowledge and data transfer sequence. An acknowledge must follow each 8-bit data transfer. After the last bit has been read, the host sends a stop condition with or without a preceding acknowledge. Figure 13. Password Protected Random Read
START Password COMMAND Read Password 7
Preliminary Information
COMBINED RANDOM/SEQUENTIAL OPERATIONS A random read and sequential read can be combined, however there are some limitations. Both password protected or non-password operations operate in the same way. After sending a random read command and reading the first byte, continued clocks will return successive addresses. However, after more than one byte of data is returned, it is not possible to initiate a new random read, without issuing a stop and starting a new command. This also allows multiple random read operations and a sequential read operation, as long as the last operation is sequential. Note: A read operation that includes a random read of the last byte in the memory or OTP arrays cannot include a sequential read operation.
Read Password 0
SDA S ACK If ACK, then Password Matches START A15 A14 A13 A12 A11 A10 A9 A8 ACK ACK ACK
Wait tWC OR Repeated ACK Polling Command
START A7 A6 A5 A4 A3 A2 A1 A0
ACK POLLING COMMAND
S NACK ACK ACK ACK Data 0
A7 A6 A5 A4 A3 A2 A1 A0
S ACK Data 0
Figure 14. Password Protected Sequential Read
START Password COMMAND Read Password 7 Read Password 0
SDA S ACK ACK ACK ACK
Wait tWC OR Repeated ACK Polling Command
If ACK, then Password Matches START ACK POLLING COMMAND
ACK
A15 A14 A13 A12 A11 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
S ACK NACK ACK ACK Data 0 Data X
13
STOP S
ACK
STOP S
X46402
Figure 15. Non-Password Protected Random Read
Preliminary Information
START A7 A6 A5 A4 A3 A2 A1 A0
START
No-Password COMMAND
A15 A14 A13 A12 A11 A10 A9 A8
SDA S ACK ACK ACK Data 0
A7 A6 A5 A4 A3 A2 A1 A0
S ACK Data 0
Figure 16. Non-Password Protected Sequential Read
START ACK No-Password COMMAND STOP S ACK ACK ACK Data 0 Data X ACK
A15 A14 A13 A12 A11 A10 A9 A8
SDA S
Figure 17. Change Passwords
START Old Password 7 Old Password 0
COMMAND
A7 A6 A5 A4 A3 A2 A1 A0
SDA S ACK ACK ACK ACK
Wait tWC OR Repeated ACK Polling Command
START
If ACK, then Password Matches
ACK POLLING COMMAND
Two bytes of "0" ACK ACK ACK
New Password 7
S NACK ACK
STOP
New Password 0
New Password 7
New Password 0
Data ACK Polling If immediate ACK, then New Password error If immediate NACK, followed by ACK after ~5ms then New Password OK
*S
ACK ACK/NoACK ACK ACK ACK
* ACK for correct password, No ACK for incorrect password
14
STOP S
X46402
Note on Read/Write Operations
No-Password Sequential Read Operation
Preliminary Information
Non- Password Protected (All of the array to none of the array)
Password Protected (None of the array to all of the array) 0000h
Notes:
Using a "password read" or a "password write" to a non-password protected area is acceptable, because the password is received and accepted prior to an address transmission. It is assumed that access to non-password protected areas is uncontrolled, so either method should work. Using a "no-password read" or a "no-password write" on a password protected area would not work. Trying to access a password protected area without the password match causes the device to return a NACK after the address. A password sequential read that starts in the password protected area can continue into and through the non-password protected area. It will not "wrap" back to address '0'. A no-password sequential read can only start in the non-password protected area and cannot "wrap" back into the protected area.
CHANGE PASSWORD COMMAND When changing a password, the Change Password command is sent to the device. The old password follows. When the old password is accepted (as indicated by the ACK Polling Command sequence), the new password is sent to the device twice, following two bytes of zero. A stop bit initiates the store of the new password. To be successful in the password change operation the first and second transmission of the new password must match and there must be exactly 16 password bytes. If this is not the case, the operation is aborted and the password remains unchanged. PASSWORDS The sequence in Figure 17 shows how to change (program) the passwords. The programming of passwords is done twice prior to the nonvolatile write cycle in order to verify that the new password is consistent. After the eight
bytes are entered in the second pass, a comparison takes place. A mismatch will cause the part to ignore the change command and enter into the standby mode. There are two ways to determine whether the operation was completed successfully. The Data ACK polling method can determine if a password has been loaded correctly, however the data ACK command must be issued less than 2ms after the stop bit. After this time, it cannot be determined if the password has been loaded correctly, without trying the new password. To determine if the new password has been loaded correctly the data ACK polling command is issued immediately following the stop bit. If it returns an ACK, then the two passes of the new password entry do not match. If it returns a "no ACK" then the passwords match and a high voltage cycle is in progress. The high voltage cycle is complete when a subsequent data ACK command returns an "ACK".
15
Password Sequential Read Operation
1FFFh
X46402
An easier way to determine that the password has been changed correctly is to read the ACK bit following the second writing of the new password. If the device returns an ACK, the password is good. A No ACK indicates something went wrong. If there was an error, the password remains unchanged. There is no way to read any of the passwords. ABSOLUTE MAXIMUM RATINGS* Temperature under Bias . . . . . . . . . . . . -65C to +135C Storage Temperature . . . . . . . . . . . . . . . -65C to +150C Voltage on any Pin with respect to VSS . . . . .-1V to +7V D.C. Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Lead Temperature (Soldering, 10 seconds) . . . . . .300C *COMMENT
Preliminary Information
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temp
Commercial Extended
Min.
0C -20C
Max.
+70C +85C
Device
X46402
Supply Voltage Limits
2.5V to 3.7V
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Symbol ICC1 Parameter VCC Supply Current (Read) VCC Supply Current (Write) VCC Supply Current (Standby) VCC Supply Current (Standby) Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Voltage Output LOW Voltage
-0.5
Limits Min. Max.
1
Units
mA
Test Conditions fSCL = 1MHz, RESET = V2FAIL = VCC w/ pull up resistor V2MON = VCC fSCL = 1MHz, RESET = V2FAIL = VCC w/ pull up resistor RST = VSS VIL = VCC x 0.1, VIH = VCC x 0.9 fSCL = 1MHz, fSDA = 400 KHz VSDA = VSCL = V2MON = VCC Other = GND or VCC-0.3V VIN = VSS to VCC VOUT = VSS to VCC VCC = 3.0V VCC = 3.0V VCC = 3.0V VCC = 3.0V IOL = 3mA
ICC2
(3)
3
mA
ISB1(1) ISB2(1) ILI ILO VIL1(2) VIH1(2) VIL2(2) VIH2(2) VOL
50 1 10 10 VCC x 0.3
A A A A V V V V V
VCC x 0.7 VCC + 0.5 -0.5 VCC x 0.1
VCC x 0.9 VCC + 0.5 0.4
16
X46402
Table 4. CAPACITANCE (TA = +25C, f = 1MHz, VCC = 3V) Symbol
COUT
(3)
Preliminary Information
Test Output Capacitance (SDA) Input Capacitance (WP, SCL, V2MON)
Max.
8 6
Units
pF pF
Conditions
VI/O = 0V VIN = 0V
CIN(3)
Notes: (1) (2) (3)
Must perform a stop command after a read command prior to measurement VIL min. and VIH max. are for reference only and are not tested. This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUIT
3V 1.3K OUTPUT 100pF
A.C. TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Level Output Load
VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5 100pF
AC CHARACTERISTICS AC Specifications (Over the recommended operating conditions) Symbol fSCL tIN tAA tBUF tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tDH tR tF SCL Clock Frequency Pulse width of spikes which must be suppressed by the input filter SCL LOW to SDA Data Out Valid Time the bus must be free before a new transmit can start Clock LOW Time Clock HIGH Time Start Condition Setup Time Start Condition Hold Time Data In Setup Time Data In Hold Time Stop Condition Setup Time Data Output Hold Time SDA and SCL Rise Time (10% to 90% of Vcc) SDA and SCL Fall Time Parameter Min
0 10 0.05 0.5 0.6 0.4 0.25 0.25 100 0 0.25 0 10 10 100 100 100 0.55
Typ(1)
Max
1000
Units
KHz ns s s s s s s ns s s ns ns ns
17
X46402
RESET AC SPECIFICATIONS Nonvolatile Write Cycle Timing Symbol
tWC(1)
Preliminary Information
Parameter
Write Cycle Time
Min.
Typ.(1)
5
Max.
10
Units
mS
Notes: 1. tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
TIMING DIAGRAMS Bus Timing
tR SCL tSU:STA SDA IN tHD:STA tF tSU:DAT tHD:DAT tSU:STO tHIGH tLOW
tAA SDA OUT
tDH
tBUF
Write Cycle Timing
SCL
SDA
8th bit of last byte
ACK tWC Stop Condition Start Condition
18
X46402
Preliminary Information
GUIDELINES FOR CALCULATING TYPICAL VALUES OF BUS PULL UP RESISTORS
V CCMAX - 0.4 R MIN = ---------------------------------------- = 1100 I OLMIN
100ns max rise time
Pull Up Resistance in K
10 8 6 4 2
V IH
RPMAX
RMAX ----------------------------------- R PMAX C BUS = Vcc 1 - e
-t
For VIH = 0.9VCC
RMIN
10 20 30 40 50
R
PMAX
= ------------------------------
tR
Bus capacitance in pF
2.3 ( C BUS )
tRMAX = maximum allowable SDA rise time
POWER-UP AND POWER-DOWN TIMING RESET Output Timing
V TRIP VCC 0 Volts t RV t PURST t PURST VTRIP
t FV t DVC
RESET
V2FAIL Output Timing
V2 TRIP 0 Volts tRB V2 TRIP t FB t DVB
V2MON
V2FAIL
19
X46402
Preliminary Information
Symbol VTRIP V2TRIP VTH V2TA tPURST tDVC(5) tDVB(5) tFV(5) tRV(5) tFB(5) tRB(5) VRVALID
Parameter RESET Trip Point Voltage V2FAIL Trip Point Voltage VTRIP Hysteresis (HIGH to LOW vs. LOW to HIGH VTRIP voltage) V2TRIP Hysteresis (HIGH to LOW vs. LOW to HIGH VTRIP voltage) Power-up Reset Timeout Detect VCC Low Voltage to Reset Output (Vcc = 2.3V) Detect V2MON Low Voltage to Reset Output (Vcc = 2.5-3.7V) VCC Fall Time VCC Rise Time V2MON Fall Time V2MON Rise Time Reset Valid VCC
Min.
2.4 1.7
Typ.
- - 40 40
Max.
3.5 3.5
Units
V V mV mV
75
150
225 65 100
ms
s s s s ns ns
100 100 500 500 1
V
Notes: (5) This parameter is periodically sampled and not 100% tested. (6) Typical values not tested.
Start Bit vs. RESET Timing
SCL
tSU:STA tSU:STO
SDA
t WDR
RESET
t WDO t RST t WDO t RST
20
X46402
RESET Output Timing Symbol Parameter Watchdog Timeout Period, WD2 = 0, WD1 = 1, WD0 = 0 WD2 = 0, WD1 = 0, WD0 = 1 WD2 = 0, WD1 = 0, WD0 = 0 WD2 = 1, WD1 = 1, WD0 = 1 WD2 = 1, WD1 = 1, WD0 = 0 WD2 = 1, WD1 = 0, WD0 = 1 WD2 = 1, WD1 = 0, WD0 = 0 SDA LOW duration (Reset the Watchdog) Reset Timeout Min.
75 225 0.5 2.5 5 10 30 400 75
Preliminary Information
Typ.
150 450 1 5 10 20 60
Max.
225 675 1.5 7.5 15 30 90
Units
ms ms sec sec sec sec sec ns
tWDO
tWDR tRST
150
225
ms
21
X46402
Preliminary Information
8-LEAD PLASTIC, TSSOP PACKAGE TYPE V ,
.025 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.114 (2.9) .122 (3.1)
.047 (1.20)
.0075 (.19) .0118 (.30)
.002 (.05) .006 (.15)
.010 (.25) Gage Plane 0- 8 .019 (.50) .029 (.75) Detail A (20X) Seating Plane
.031 (.80) .041 (1.05)
See Detail "A"
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
22
X46402
ORDERING INFORMATION VCC Range
2.5-3.7V 2.5-3.7V 2.5-3.7V
Preliminary Information
VTRIP
3.1 3.1 2.9
V2TRIP
2.6 1.7 2.3
Package
8L TSSOP 8L TSSOP 8L TSSOP
Operating Temperature Range
0C-70C -20C-85C 0C-70C -20C-85C 0C-70C -20C-85C
Part Number
X46402V8-3.1 X46402V8E-3.1 X46402V8-3.1A X46402V8E-3.1A X46402V8-2.9 X46402V8E-2.9
Notes: Tolerance for Vtrip and V2trip are +/-5%
PART MARK CONVENTION 8-Lead TSSOP EYWW XXXX XX VTRIP 4642 AR = 4642 AS = 4642 AT = 4642 AU = 4642 AV = 4642 AW = 3.1 3.1 3.1 3.1 2.9 V2TRIP 2.6 2.6 1.7 1.7 2.3 2.3 Temp 0 to 70 C -20 to 85C 0 to 70 C -20 to 85C 0 to 70 C -20 to 85C
2.9
LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
2.
23

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